The paper deals with a multiple fault diagnosis of DC transistor circuits with limited accessible terminals for measurements. An algorithm for identifying faulty elements and evaluating their parameters is proposed. The method belongs to the category of simulation before test methods. The dictionary is generated on the basis of the families of characteristics expressing voltages at test nodes in terms of circuit parameters. To build the fault dictionary the n-dimensional surfaces are approximated by means of section-wise piecewise-linear functions (SPLF). The faulty parameters are identified using the patterns stored in the fault dictionary, the measured voltages at the test nodes and simple computations. The approach is described in detail for a double and triple fault diagnosis. Two numerical examples illustrate the proposed method.
This article presents combined approach to analog electronic circuits testing by means of evolutionary methods (genetic algorithms) and using some aspects of information theory utilisation and wavelet transformation. Purpose is to find optimal excitation signal, which maximises probability of fault detection and location. This paper focuses on most difficult case where very few (usually only input and output) nodes of integrated circuit under test are available.