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Abstract

High voltage direct current (HVDC) emergency control can significantly improve the transient stability of an AC/DC interconnected power grid, and is an important measure to reduce the amount of generator and load shedding when the system fails. For the AC/DC interconnected power grid, according to the location of failure, disturbances can be classified into two categories: 1) interconnected system tie-line faults, which will cause the power unbalance at both ends of the AC system, as a result of the generator rotor acceleration at the sending-end grid and the generator rotor deceleration at the receiving-end grid; 2) AC system internal faults, due to the isolation effect of the DC system, only the rotor of the generator in the disturbed area changes, which has little impact on the other end of the grid. In view of the above two different locations of disturbance, auxiliary power and frequency combination control as well as a switch strategy, are proposed in this paper. A four-machine two-area transmission system and a multi-machine AC/DC parallel transmission system were built on the PSCAD platform. The simulation results verify the effectiveness of the proposed control strategy.
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Abstract

In this paper, the PLC-based (Programmable Logic Controller) industrial implementation in the form of the general-purpose function block for ADRC (Active Disturbance Rejection Controller) is presented. The details of practical aspects are discussed because their reliable implementation is not trivial for higher order ADRC. Additional important novelties discussed in the paper are the impact of the derivative backoff and the method that significantly simplifies tuning of higher order ADRC by avoiding the usual trial and error procedure. The results of the practical validation of the suggested concepts complete the paper and show the potential industrial applicability of ADRC.
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Abstract

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don’t disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-s. Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.
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