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Abstract

Power electronic circuits (PECs) are prone to various failures, whose classification is of paramount importance. This paper presents a data-driven based fault diagnosis technique, which employs a support vector data description (SVDD) method to perform fault classification of PECs. In the presented method, fault signals (e.g. currents, voltages, etc.) are collected from accessible nodes of circuits, and then signal processing techniques (e.g. Fourier analysis, wavelet transform, etc.) are adopted to extract feature samples, which are subsequently used to perform offline machine learning. Finally, the SVDD classifier is used to implement fault classification task. However, in some cases, the conventional SVDD cannot achieve good classification performance, because this classifier may generate some so-called refusal areas (RAs), and in our design these RAs are resolved with the one-against-one support vector machine (SVM) classifier. The obtained experiment results from simulated and actual circuits demonstrate that the improved SVDD has a classification performance close to the conventional one-against-one SVM, and can be applied to fault classification of PECs in practice.
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Abstract

This paper presents a novel strategy of fault classification for the analog circuit under test (CUT). The proposed classification strategy is implemented with the one-against-one Support Vector Machines Classifier (SVC), which is improved by employing a fault dictionary to accelerate the testing procedure. In our investigations, the support vectors and other relevant parameters are obtained by training the standard binary support vector machines. In addition, a technique of radial-basis-function (RBF) kernel parameter evaluation and selection is invented. This technique can find a good and proper kernel parameter for the SVC prior to the machine learning. Two typical analog circuits are demonstrated to validate the effectiveness of the proposed method.
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Abstract

In order to make the analog fault classification more accurate, we present a method based on the Support Vector Machines Classifier (SVC) with wavelet packet decomposition (WPD) as a preprocessor. In this paper, the conventional one-against-rest SVC is resorted to perform a multi-class classification task because this classifier is simple in terms of training and testing. However, this SVC needs all decision functions to classify the query sample. In our study, this classifier is improved to make the fault classification task more fast and efficient. Also, in order to reduce the size of the feature samples, the wavelet packet analysis is employed. In our investigations, the wavelet analysis can be used as a tool of feature extractor or noise filter and this preprocessor can improve the fault classification resolution of the analog circuits. Moreover, our investigation illustrates that the SVC can be applicable to the domain of analog fault classification and this novel classifier can be viewed as an alternative for the back-propagation (BP) neural network classifier.
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Abstract

Fault detection and location are important and front-end tasks in assuring the reliability of power electronic circuits. In essence, both tasks can be considered as the classification problem. This paper presents a fast fault classification method for power electronic circuits by using the support vector machine (SVM) as a classifier and the wavelet transform as a feature extraction technique. Using one-against-rest SVM and one-against-one SVM are two general approaches to fault classification in power electronic circuits. However, these methods have a high computational complexity, therefore in this design we employ a directed acyclic graph (DAG) SVM to implement the fault classification. The DAG SVM is close to the one-against-one SVM regarding its classification performance, but it is much faster. Moreover, in the presented approach, the DAG SVM is improved by introducing the method of Knearest neighbours to reduce some computations, so that the classification time can be further reduced. A rectifier and an inverter are demonstrated to prove effectiveness of the presented design.
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