In this paper we discuss some physical limits for scaling of transistors and conducting paths inside of semiconductor integrated circuits (ICs). Since 40 years only a semiconductor technology, mostly the CMOS and the TTL technologies, are used for fabrication of integrated circuits on an industrial scale. Miniaturization of electronic devices in integrated circuits has technological limits and physical limits as well. In 2010 best parameters of commercial ICs shown the Intel Core i5-670 processor manufactured in the technology of 32 nm. Its clock frequency in turbo mode is 3.73 GHz. A forecast of the development of the semiconductor industry (ITRS 2011) predicts that sizes of electronic devices in ICs circuits will be smaller than 10 nm in the next 10 years. At least 5 physical effects should be taken into account if we discuss limits of scaling of integrated circuits.
Evolution of many high technologies such as microelectronics, microsystem technology and nanotechnology involves design, application and testing of technical structures, whose size is being decreased continuously. Scanning probe microscopes (SPM) are therefore increasingly used as diagnostic and measurement instruments. Consequently the demand for standardized calibration routines for this kind of equipment rises. Up to now, there has been no in generally accepted guideline on how to perform SPM calibration procedure. In this article we discuss calibration scheme and focus on several critical aspects of SPM characterization e.g. the determination of the static and dynamic physical properties of the cantilever, the influence factors which need to be considered when plotting a scheme for the calibration of the force and displacement sensitivity.