The aim of this publication is to design a procedure for the synthesis of an IDT (interdigital transducer) with diluted electrodes. The paper deals with the surface acoustic waves (SAW) and the theory of synthesis of the asymmetrical delay line with the interdigital transducer with diluted electrodes. The authors developed a theory, design, and implementation of the proposed design. They also measured signals. The authors analysed acoustoelectronic components with SAW: PLF 13, PLR 40, delay line with PAV 44 PLO. The presented applications have a potential practical use.
The paper deals with the issue of constructing delay lines on the basis of surface acoustic waves and their application to single-mode oscillators. As a result of a theoretical analysis concrete delay lines are proposed. In the contribution, there is presented a theory of designing a symmetrical mismatched and matched delay line for a single-mode oscillator of electrical signals on the basis of which there were designed and fabricated acoustic-electronic components for sensors of non-electrical quantities. From the experimental results it can be stated that all of six designed and fabricated delay lines can be effectively used in the construction of single-mode oscillators.
The paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).
The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.
Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.