This paper deals with multiple soft fault diagnosis of nonlinear analog circuits comprising bipolar transistors characterized by the Ebers-Moll model. Resistances of the circuit and beta forward factor of a transistor are considered as potentially faulty parameters. The proposed diagnostic method exploits a strongly nonlinear set of algebraic type equations, which may possess multiple solutions, and is capable of finding different sets of the parameters values which meet the diagnostic test. The equations are written on the basis of node analysis and include DC voltages measured at accessible nodes, as well as some measured currents. The unknown variables are node voltages and the parameters which are considered as potentially faulty. The number of these parameters is larger than the number of the accessible nodes. To solve the set of equations the block relaxation method is used with different assignments of the variables to the blocks. Next, the solutions are corrected using the Newton-Raphson algorithm. As a result, one or more sets of the parameters values which satisfy the diagnostic test are obtained. The proposed approach is illustrated with a numerical example.
This paper is devoted to multiple soft fault diagnosis of analog nonlinear circuits. A two-stage algorithm is offered enabling us to locate the faulty circuit components and evaluate their values, considering the component tolerances. At first a preliminary diagnostic procedure is performed, under the assumption that the non-faulty components have nominal values, leading to approximate and tentative results. Then, they are corrected, taking into account the fact that the non-faulty components can assume arbitrary values within their tolerance ranges. This stage of the algorithm is carried out using the linear programming method. As a result some ranges are obtained including possible values of the faulty components. The proposed approach is illustrated with two numerical examples.
The paper deals with fault diagnosis of nonlinear analogue integrated circuits. Soft spot short defects are analysed taking into account variations of the circuit parameters due to physical imperfections as well as self-heating of the chip. A method enabling to detect, locate and estimate the value of a spot defect has been developed. For this purpose an appropriate objective function was minimized using an optimization procedure based on the Fibonacci method. The proposed approach exploits DC measurements in the test phase, performed at a limited number of accessible points. For illustration three numerical examples are given.
The paper deals with a multiple fault diagnosis of DC transistor circuits with limited accessible terminals for measurements. An algorithm for identifying faulty elements and evaluating their parameters is proposed. The method belongs to the category of simulation before test methods. The dictionary is generated on the basis of the families of characteristics expressing voltages at test nodes in terms of circuit parameters. To build the fault dictionary the n-dimensional surfaces are approximated by means of section-wise piecewise-linear functions (SPLF). The faulty parameters are identified using the patterns stored in the fault dictionary, the measured voltages at the test nodes and simple computations. The approach is described in detail for a double and triple fault diagnosis. Two numerical examples illustrate the proposed method.
Field programmable analog arrays (FPAA), thanks to their flexibility and reconfigurability, give the designers quite new possibilities in analog circuit design. The number of both academic projects on FPAA and applications of commercially available programmable devices is still growing. This paper explores the properties and parameters of two most popular FPAA circuits: the AnadigmVortex AN221E04 and AnadigmApex AN231E04 from the Anadigm company. The research conducted by the authors led to the discovery of some undocumented features of these devices. Several applications for audio processing were built and tested. The results show that these circuits can be used in medium-demanding audio applications. Thanks to dynamic reconfigurability, they also allow to build an universal analog audio signal processor. These circuits can also act as a versatile platform for rapid prototyping and educational purposes.
In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.
This paper presents methods for optimal test frequencies search with the use of heuristic approaches. It includes a short summary of the analogue circuits fault diagnosis and brief introductions to the soft computing techniques like evolutionary computation and the fuzzy set theory. The reduction of both, test time and signal complexity are the main goals of developed methods. At the before test stage, a heuristic engine is applied for the principal frequency search. The methods produce a frequency set which can be used in the SBT diagnosis procedure. At the after test stage, only a few frequencies can be assembled instead of full amplitude response characteristic. There are ambiguity sets provided to avoid a fault tolerance masking effect.
Correct incipient identification of an analog circuit fault is conducive to the health of the analog circuit, yet very difficult. In this paper, a novel approach to analog circuit incipient fault identification is presented. Time responses are acquired by sampling outputs of the circuits under test, and then the responses are decomposed by the wavelet transform in order to generate energy features. Afterwards, lower-dimensional features are produced through the kernel entropy component analysis as samples for training and testing a one-against-one least squares support vector machine. Simulations of the incipient fault diagnosis for a Sallen-Key band-pass filter and a two-stage four-op-amp bi-quad low-pass filter demonstrate the diagnosing procedure of the proposed approach, and also reveal that the proposed approach has higher diagnosis accuracy than the referenced methods.
This article presents combined approach to analog electronic circuits testing by means of evolutionary methods (genetic algorithms) and using some aspects of information theory utilisation and wavelet transformation. Purpose is to find optimal excitation signal, which maximises probability of fault detection and location. This paper focuses on most difficult case where very few (usually only input and output) nodes of integrated circuit under test are available.
A simple analog circuit is presented which can play a neuron role in static-model-based neural networks implemented in the form of an integrated circuit. Operating in a transresistance mode it is suited to cooperate with transconductance synapses. As a result, its input signal is a current which is a sum of currents coming from the synapses. Summation of the currents is realized in a node at the neuron input. The circuit has two outputs and provides a step function signal at one output and a linear function one at the other. Activation threshold of the step output can be conveniently controlled by means of a voltage. Having two outputs, the neuron is attractive to be used in networks taking advantage of fuzzy logic. It is built of only five MOS transistors, can operate with very low supply voltages, consumes a very low power when processing the input signals, and no power in the absence of input signals. Simulation as well as experimental results are shown to be in a good agreement with theoretical predictions. The presented results concern a 0.35 1m CMOS process and a prototype fabricated in the framework of Europractice.
In order to make the analog fault classification more accurate, we present a method based on the Support Vector Machines Classifier (SVC) with wavelet packet decomposition (WPD) as a preprocessor. In this paper, the conventional one-against-rest SVC is resorted to perform a multi-class classification task because this classifier is simple in terms of training and testing. However, this SVC needs all decision functions to classify the query sample. In our study, this classifier is improved to make the fault classification task more fast and efficient. Also, in order to reduce the size of the feature samples, the wavelet packet analysis is employed. In our investigations, the wavelet analysis can be used as a tool of feature extractor or noise filter and this preprocessor can improve the fault classification resolution of the analog circuits. Moreover, our investigation illustrates that the SVC can be applicable to the domain of analog fault classification and this novel classifier can be viewed as an alternative for the back-propagation (BP) neural network classifier.